Hybrid Copper-Graphene Package Interconnects for Channel Loss Improvement in High-Speed Serial Interfaces

Abstract

Data rates in high-speed interfaces like upcoming PCIe Gen6, SERDES, Ethernet are continuously increasing, and the design specifications are becoming more stringent to ensure required performance. Any small variation in the specifications will have significant impact on signal integrity and affect the performance. This means that the total insertion loss, ISI, non-ISI jitter in the entire interconnect should be improved.IC package plays a key role in signal integrity of the high-speed signal and there is a need to have low loss channel. Standards like PCIe have a loss requirement of 4 dB combining silicon and package, in case of non-root complex. Recent developments suggest new design trends for multi-chiplets in a single package with increasing package sizes, which can make it extremely difficult to predict insertion loss specifications. Conductivity, dielectric properties, and loss tangent drives the overall loss per unit length and the current low-loss materials have insertion loss of around 1 dB per 10 mm. While many advances have been reported in the literature, scope for improvement exists and conventional approaches of lowering DF of dielectric material or reducing the surface roughness of Copper have helped but are not adequate for the demands of high-speed interconnects. This paper proposes a novel approach by using hybrid Copper-Graphene package interconnects, which helps in reducing signal losses and improves the overall performance of the system.