Hurdle model with random effects for the study of copper hillocks growth in integrated circuits manufacturing

Abstract

During manufacturing process of integrated circuits (ICs), copper hillocks grow vertically from the metal lines and cause inter layer metallic shorts and reliability issues. Uncovering the impact of design factors on the formation of copper hillocks is of vital importance for reducing shorts and improving the ICs design. An experiment was conducted to collect the wafer defective counts (shorts) data for different design settings. Our preliminary analysis identified two characteristics of the observed defective counts: zero-inflation and multi-level clustering/variability (layer-to-layer, wafer-to-wafer, lot-to-lot). In this work, a hurdle model with random effect that handles both these complex characteristics together is adopted and provides us with a better understanding of how to monitor and reduce the effects of copper hillocks by recommending design rules.