A Multilevel Zero-Inflated Model for the Study of Copper Hillocks Growth in Integrated Circuits Manufacturing

Abstract

As integrated circuits (ICs) are rapidly migrating to smaller feature sizes, copper hillocks growing vertically from the copper back-end interconnects may cause inter layer metallic shorts and reliability issues. Uncovering the impact of design factors on the formation of copper hillocks is of importance for reducing the number of shorts and improving the ICs design. The purpose of this paper is twofold: 1) to experimentally investigate the mechanisms for hillock formation in a manufacturing environment and to develop a statistical model incorporating these features for more accurate predictions and 2) to determine optimal design settings to minimize hillock related short-circuits. In this paper, we describe our approach to collecting the data and our statistical model for the analysis of copper hillocks growth on ICs. To capture the low failure observations and multilevel variations, we extend the zero-inflated model, which assumes the system randomly shifts between a zero state and a count state, to a multilevel model for our problem. We first analyze the mechanism causing the zero state to determine at which level the state shift occurs. Then, the distribution of the count state is derived based on the hillocks number and the hillock height. Finally, flexible random effects distributions are incorporated to model the non-normal variations. Our analysis of the process and development of the model enable the capture of the unique characteristics of the process, and provide a platform to understand the factors governing the growth of copper hillocks in a manufacturing environment that would not have been possible if standard existing models have been applied. This has led to some previously unknown insights on the physical hillocks growth process.