HSQ hybrid lithography for 20 nm CMOS devices development

Abstract

This paper reports the lithographic development on 8 in. silicon wafers for 20 nm CMOS devices using a hydrogen silsesquioxane (HSQ) hybrid lithography process. The method relies on splitting the pattern into high-resolution and low-resolution components at the same level. Geometries lower than 40 nm are exposed with HSQ ebeam process, geometries between 40 and 250 nm with a chemical amplified resist (CAR) ebeam process and the remaining with a CAR deep UV process. Using this technique, we can produced 20 nm structures with an exposure time drastically lower than using only a single HSQ ebeam lithography process. Finally, a pattern transfer capability of a 20 nm isolated line into a polysilicon layer is presented.