Abstract
In this paper, we present a fast hybrid priority queue architecture intended for scheduling and prioritizing packets in a network data plane. Due to increasing traffic and tight requirements of high-speed networking devices, a high capacity priority queue, with constant latency and guaranteed performance is needed. We aim at reducing latency to best support the upcoming 5G wireless standards. The proposed hybrid priority queuing system (HPQS) enables pipelined queue operations with almost constant time complexity in practice. The proposed architecture is implemented in C++, and is synthesized with the Vivado High-Level Synthesis (HLS) tool. Two configurations are proposed. The first one is intended for scheduling with a multi-queuing system for which implementation results of 64 up to 512 independent queues are reported. The second configuration is intended for large capacity priority queues, that are placed and routed on a ZC706 board and a XCVU440-FLGB2377-3-E Xilinx FPGA supporting a total capacity of 1/2 million packet tags. The reported results are compared across a range of priority queue depths and performance metrics with existing approaches. The proposed HPQS supports links operating at 40 Gb/s.
Highlights
In modern routers, switches, line cards, etc., we find Network Processing Units (NPUs) [1]–[3]
It should be noted that packet classification is not discussed further in this paper, as we focus on strict priority scheduling and high capacity priority queuing with the proposed hybrid priority queuing system (HPQS) architecture in field-programmable gate array (FPGA)
PLACEMENT AND ROUTING RESULTS The proposed HPQS was implemented on a Xilinx Zynq-7000 ZC706 board and on a XCVU440 Virtex UltraScale device, using Vivado tool with the Explore directive enabled
Summary
Switches, line cards, etc., we find Network Processing Units (NPUs) [1]–[3] They provide dedicated processing stages for traffic management and buffering. NETWORK SWITCHES Today’s switches provide various sets of functionalities, from parsing, classification, scheduling and buffering of the network traffic These functionalities can be supported by transformations applied to the traffic from the moment packets are received on input ports up to their transmission through destination ports. An example of such switches in the literature is the Broadcom’s Trident II series [16]. This translates into about 1 – 4 billion packets per second
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