Hot-electron-induced degradation in high-voltage submicron DMOS transistors

Abstract

The degradation induced by hot-electrons is investigated in small-size lateral and vertical DMOS transistors with voltage rating from 16 to 60 V integrable in a multi-power Bipolar-CMOS-DMOS mixed process with 1.2 /spl mu/m minimum lithography. Dedicated hot-electron tests are necessary to define the maximum operating drain and gate voltage of the devices. An empirical extrapolation model and a simplified scheme for accelerated qualification/reliability tests are proposed allowing one to define the hot-electron-limited safe operating area of DMOS transistors. A quasi-static extension of the model accounts for the hot-electron-induced degradation under a variety of dynamic bias-stress conditions.