Hot-Carrier-Induced On-Resistance Degradation of n-Type Lateral DMOS Transistor With Shallow Trench Isolation for High-Side Application

Abstract

In this paper, the hot-carrier-induced on-resistance degradation of the n-type lateral DMOS (nLDMOS) transistor with shallow trench isolation (STI) for high-side application has been experimentally investigated. We have found that the dominant on-resistance degradation mechanism of the high-side nLDMOS device (HS-nLDMOS) is the interface state generation at the STI corner. Moreover, the degradation of the on-resistance for high-side application (R on,hs, measured at high drain voltage and high source voltage) is much larger than that for low-side application (R on,ls, measured at low drain voltage and grounded source). This is because the current distribution under the R on,hs state is closer to the damaged STI corner than that under the R on,ls state due to the larger potential difference between the drain and the substrate. Therefore, the on-resistance degradation of the HS-nLDMOS must be measured by using the R on,hs condition, to evaluate the lifetime of the device accurately.