Hot-Carrier-Induced Degradation and Optimization for 700-V High-Voltage Lateral DMOS by the AC Stress

Abstract

Because of the extremely narrow dc thermal safe operating area for 700-V high-voltage lateral double-diffused MOS (LDMOS) transistor, the gate duty-cycle-accelerated ac stress was adopted to investigate its hot-carrier-induced degradations. It is found that there are different degradation mechanisms with different amplitudes of ac gate stress, including the maximum operating gate voltage ( ${V}_{{\text {gmax}}}$ ) stress and the maximum substrate current ( ${I}_{{\text {submax}}}$ ) stress. For the ${V}_{{\text {gmax}}}$ condition, the ON-resistance ( ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) decreases first and increases finally, which is attributed to two competitive degradation mechanisms. One is the hot holes injection at the bird’s beak during the gate pulse edges, and the other one is the hot electrons injection nearby the drain during the high state level of gate pulse. However, for the ${I}_{{\text {submax}}}$ stress, the dramatical injection of hot electrons nearby the source-metal edge during the high state level of gate pulse is always the main degradation mechanism, resulting in a monotonous increase of $\text {R}_{{ \mathrm{\scriptscriptstyle ON}}}$ . Moreover, the threshold voltage ( ${V}_{{\text {th}}}$ ) degradations could be neglected due to the intact channel region under the ${V}_{{\text {gmax}}}$ and ${I}_{{\text {submax}}}$ conditions. In this way, the ${I}_{{\text {submax}}}$ condition is regarded as the worst stress, and an improved device with a linear-doped buried-p-well (BP) structure beneath the P-body has been proposed to restrain the degradation under the worst stress condition.