Hot-carrier induced degradation and recovery in polysilicon-emitter bipolar transistors

Abstract

The hot-carrier induced degradation in submicron polysilicon-emitter NPN bipolar transistors with different emitter geometries and its post-stress reversibility have been investigated in detail. We show that the hot-carrier induced degradation during reverse emitter–base (EB) bias stressing can alter the EB junction, as well as the collector–base junction region. Oxide/silicon interface traps and positive charged defects are generated by the hot-carrier injection, both of which cause an increase in the low bias base current, and consequently degradation in the current gain. Our results confirm that the oxide/silicon interface traps generated by electrical stressing are located in the same region as those present in unstressed devices––around the emitter perimeter. The hot-carrier induced changes are not stable even at room temperature, and are partially reversed by annealing at 300 °C, indicating the existence of both a reversible component, with a broad distribution of annealing activation energies, and an irreversible component. We suggest that more than one microscopic process determines the hot-carrier induced degradation in devices. Which process plays a dominant role in a given device may be dependent on device technologies employed and stressing conditions.