HLS-Based Performance and Resource Optimization of Cryptographic Modules

Abstract

High-level Synthesis (HLS) significantly enhances the development of multi-processor systems-on-chip by simplifying FPGA module development. In this work, we use HLS to develop multiple approaches of microarchitectures for Advanced Encryption Standard (AES) cryptographic (crypto) FPGA modules and compare them. Our approaches mostly focus on the application of parallelism when using HLS for automatic Register-Transfer Level (RTL) design generation. We compare the result of our approaches with a traditionally developed RTL implementation concerning maximum throughput and resource utilization. We also do a comparison to published state-of-the-art RTL-code-based development, and other HLS-based crypto module development approaches. By using HLS, we can reduce development time compared to the traditional RTL-code-based development. Furthermore, we improve the theoretical performance of our crypto module to achieve a maximum clock frequency of up to 343 MHz and a data rate of 43.90 Gbps (128-bit processing per clock cycle). Alternatively, the resource utilization of FPGA can be optimized to be lower than for the traditionally-developed implementation. As future work, the diversification of resource utilization and other approaches presented in this paper may be used to reduce side-channel leakage of signal properties.