High-Voltage Gain CMOS Charge Pump at Subthreshold Operation Regime for Low Power Applications

Abstract

This paper presents an enhanced complimentary metal oxide semiconductor (CMOS) charge pump (CP) circuit with improved gain and efficiency by dynamically controlling substrate and gate terminals of PMOS transistor. The proposed novel charge pump provides good performance even at low voltage. But, the efficiency of the charge pump circuit is being influenced by body effect and threshold voltage as the number of stage increases. Hence, numerous charge pump strategies are used to minimize the effect of threshold voltage and body effect. In this paper, the above-mentioned issues are overcome by implementing charge pump circuit in 180-nm standard in Cadence Virtuoso operated at low-voltage CMOS technology. From the result obtained, it is analyzed that the proposed CMOS charge pump achieves an improved voltage conversion ratio, efficiency and low operating voltage as compared to existing conventional CMOS charge pumps.