Abstract
A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current- mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
