Abstract
A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-/spl mu/m CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.
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