High-speed serial interconnect transceiver: Applications and design

Abstract

In this paper, the design and applications of high-speed interconnect transceivers are presented. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Channel modeling and analysis are very critical in high-speed serial transceiver design. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in the paper. Implementation examples of key building blocks for high-speed serial transceiver in deep sub-micron CMOS logic process are also introduced.