Abstract
In this paper, the equalization techniques for high-speed interconnect transceivers are discussed. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in the paper. Implementation examples of key building blocks for high-speed serial transceiver in deep sub-micron CMOS logic process are also introduced.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
