High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

Abstract

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method.