High-Speed Loop Unrolled Grain Architecture in Reconfigurable Hardware

Abstract

Crypto core finds implementaions in software, Application Specific Integrated Circuit (ASIC), and Field Programmable Gate Array (FPGA). The crypto software programs achieve very less throughput, whereas ASIC implementations serve reasonably cost-effective design with efficient performance. In ASIC platform, once the design is implemented, it is not possible to alter those circuit connection, whereas FPGA is a flexible solution which can be reconfigured in the field. For huge number of gate applications, FPGA is cost-effective compared to ASIC and software implementation. This submission explores FPGA design spaces of Grain crypto hardware core. The article implements seven loop unrolled architectures which are implemented in Xilinx Zynq FPGA using VHDL language in Vivado Design Suit. The results show that three basic systems’ parameters such as resource usage, power consumption, and throughput of proposed implementation are satisfactorily optimized compared to existing literature.