High-speed linear CCD sensor with pinned photodiode photosite for low-lag and low-noise imaging

Abstract

Photodiode devices, in which the photosite consists of a reverse biased pn diode, have excellent quantum efficiencies at visible wavelengths and in the UV. However, they display high levels of dark and bright image lag, and high levels of fixed pattern noise (FPN) when operated with electronic shuttering. We have addressed these performance issues by replacing the photodiode photosites with pinned photodiode (PPD) photosites. In the PPD the n+ region of the conventional photodiode is replaced by a n region and a shallow highly doped p region - the surface potential in the photosite is pinned such that the photosite behaves as an ungated buried channel well. The high quantum efficiencies associated with photodiodes are maintained while allowing for large reductions in image lag and fixed pattern noise. We have developed PPD processes for two different photosite architectures. In the first architecture, charge is generated in the PPD and immediately spills to an adjacent gated integration well. In the second architecture, the charge is generated and stored in the PPD. Each of the architectures can be configured to allow for antiblooming/electronic shuttering. Both of the PPD processes and their associated architectures have been characterized, and order of magnitude reductions in image lag have been observed for PPD photosites relative to conventional photodiodes. No degradation in QE, PRNU, or well capacity has been observed. One of the PPD processes has been implemented in a family of high sped, quad output, linear sensors with 200 MHz data rates. Performance results are presented.