High-Speed CMOS Three-Stage Amplifier Based on Feedback Attenuation

Abstract

This paper presents a new and simple frequency compensation scheme for multistage CMOS operational transconductance amplifiers (OTAs). In this work, by applying a differential block frequency compensation (DBFC) technique to a compensation network of three-stage OTA, the dominant pole is drastically improved independent from the DC gain path. The DBFC introduces amplified signal directly to the second-stage output through the compensation capacitor. The signal injection increases operational frequency range while just a single and small value capacitor is used as the Miller capacitor, which leads to considering the proposed configuration as a low die area occupation and high-speed amplifier. The simulation results show with the same capacitive load and power dissipation the gain bandwidth (GBW) frequency can be improved considerably compared to conventional nested Miller compensation. The presented circuit is simulated in a 0.18[Formula: see text][Formula: see text]m CMOS technology with a 1.8[Formula: see text]V supply voltage. According to the results, the proposed circuit shows 102[Formula: see text]dB, 105[Formula: see text]MHz, and 343[Formula: see text][Formula: see text]W as the DC gain, GBW, and power consumption, respectively.