Abstract
A pipelined four-phase logic circuit called the CMOS capacitor coupling logic (C/sup 3/L) circuit is proposed. The operation of the pipelined system is described. A folding technique is used for the XOR gate design. A carry look-ahead adder (CLA) is designed using the capacitor coupling technique. Using the technique, the device count and the power dissipation can be reduced. The simulation of a full adder and a CLA in 0.35 /spl mu/m process shows that the maximum operating speed can reach 400 MHz.
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