High-speed baud-rate clock and data recovery

Abstract

This work focuses on the practical aspects of high speed baud-rate clock and data recovery (CDR). Baud-rate CDRs reduce the number of clock sampling phases compared to edge-sample phase detector (PD) based CDRs. These CDRs do not require transition samples in addition to the data samples for timing information. Baud-rate CDRs exploit other properties of the incoming data for timing information. Typical baud-rate CDRs rely on specific patterns for timing recovery. However, minimum mean squared error (MMSE) PD based CDRs rely on the slope and error information for timing recovery and therefore are not pattern dependent. A modified form of MMSE simplifies the conventional MMSE algorithm for NRZ data such that only the slope information is required. Three different slope detection techniques are presented: one with an integrate and dump, one with an active filter and the other with a passive filter. The passive filter is most suitable for slope detection at high-speeds. A prototype passive filter in 0.18 pin CMOS is implemented and tested upto 10-Gb/s and consumes 21.6 mW including a pre-amplifier stage. A half-rate modified MMSE PD-based CDR architecture using the passive slope detector is proposed and compared with a conventional edge-sample PD based CDR using identical circuit blocks. Simulations predict improved jitter performance for the proposed technique and similar power consumptions for the two techniques.