36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector

Abstract

A 36-Gb/s clock and data recovery (CDR) circuit with a simple passive loop filter is presented. By combining the passive load for output magnitude generation in the phase detector with a passive loop filter, the cutoff frequency and high-frequency response in the loop filter can be controlled independently. The CDR consists of a half-rate decision circuit that provides higher speed operation. To confirm the validity of the proposed topology, we fabricated a 36-Gb/s CDR IC with the 65-nm MOSFET process. It provides an 18-GHz extracted clock (half rate) signal and 18-Gb/s recovered date (1:2DEMUX output). The measured jitter was lower than 1.15 ps rms. The area of chip, including an I/O buffer circuit, was 1 mm2, and the power consumption was 290 mW.