High-resolution defect metrology for silicon BARC analysis

Abstract

Measuring coating defects on two or more blanket film layers is difficult and can be misleading due to reflectivity changes from the bottom layer, and surface roughness not present when the substrate is only polished silicon. To improve signal-to-noise ratio and establish a lower limit for particle size detection, polystyrene latex (PSL) spheres are deposited on the film stack. Particles as small as 54 nm were detectable on a stack 330-nm thick using a Hitachi LS Series Surface Scanning Inspection System (SSIS) and RS5500 Defect Review Scanning Electron Microscope (DRSEM). These systems have advanced capabilities enabling automated detection, classification, and characterization of defects down to 30 nm or smaller on some substrates and films. Haze wafer maps are related to surface roughness and reflectivity and show unusual asymmetries possibly caused by dispense problems or exhaust flow patterns during baking. These maps can be helpful to find problems in the coating system, even if film thickness is on target. Preliminary testing results are presented for a typical trilayer pattern stack for high-resolution 193-nm patterning consisting of a silicon spinon hardmask (HM) layer on top of a spin-on carbon (SOC) layer. The majority of the defects were caused by bubble formation within the HM that was modulated by process conditions used for these tests. A higher spin speed for the HM coating produced lower defects, most likely due to a thinner film with less trapped solvent during baking, but this effect will require more study, as it could also be due to a faster evaporation rate caused by higher airflow. Pre-wet, spin time, and bake temperature did not produce significant effects within these tests, but showed trends requiring further study. These advanced spin-on HM materials can be applied as thin as 15 to 20 nm due to their high etch selectivity. With the use of such high-resolution defect metrology, very subtle chemical interactions and process effects can be examined to find the ideal process conditions for both the SOC and HM layers.