High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System

Pavel Lyakhov,Georgii Valuev,Maria Valueva,Nikolai Nagornov

doi:10.1109/access.2020.3038496

Pavel Lyakhov, Georgii Valuev + Show 2 more

Open Access

https://doi.org/10.1109/access.2020.3038496

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Journal: IEEE Access	Publication Date: Jan 1, 2020
Citations: 40	License type: CC BY 4.0

Affiliation: North-Caucasus Federal University

Abstract

The article proposes new modified Multiply-Accumulate (MAC) units called truncated MAC units and using residue number system (RNS) with moduli of a special form. The effectiveness of the proposed blocks is verified by hardware implementation of digital filtering. The paper presents a comparative theoretical analysis of the proposed approach using the RNS and the known methods using the conventional positional number system (PNS) and RNS. Moreover, in the paper, a hardware simulation on FPGA of digital filters using arithmetic of RNS is performed, and comparison with the known implementations are realized. It is shown that using proposed approach based on RNS makes it possible to increase the frequency of digital filters by about 4 times, and reduce the hardware costs by 3 times, in comparison with the use of the traditional positional number system. Comparison proposed method and known methods based on RNS shows that using proposed method allows to increase the frequency by about 2-6 times, and reduce the hardware costs by 1.5-5 times, with increasing power consumption by 23%. Obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC, etc.) for solving practical problems such as noise reduction, amplification and suppression of frequencies, interpolation, decimation, equalization, and many others.

Highlights

Digital filtering is the core of digital signal processing, since it underlies the solution of most practical problems in this area: noise reduction [1], amplification and suppression of frequencies [2], interpolation [3], decimation [4], equalization [5] and many others
The paper proposes the implementation of digital filtering in Residue number system (RNS) with special moduli form using modified MAC unit truncated MAC (TMAC)
According to the theoretical analysis, in general, more RNS moduli provide a greater advantage in terms of speed and savings in hardware costs compared to the implementation of digital filters (DF) in positional number system (PNS)

Summary

INTRODUCTION

Digital filtering is the core of digital signal processing, since it underlies the solution of most practical problems in this area: noise reduction [1], amplification and suppression of frequencies [2], interpolation [3], decimation [4], equalization [5] and many others. In the paper [10], comparative analysis of hardware implementations of digital signal processing devices in RNS and in the conventional two’s complement system is performed. In the paper [14] the hardware implementation of FIR DF using RNS with moduli set {2k − 1, 2k, 2k + 1}, k ∈ N, is proposed. We propose new modular truncated MAC (TMAC) units using RNS moduli of special forms 2k , k ∈ N and 2k − 1, k ∈ N, k > 1, to increase speed and save hardware costs and power consumption. The article analyzes and presents the results of hardware simulation on FPGA FIR DF, using proposed modular TMAC unit, in the RNS and in the traditional positional number system (PNS).

BACKGROUND

PROPOSED ARCHITECTURE OF FIR DIGITAL FILTER WITH MODIFIED MAC UNIT

THEORETICAL ANALYSIS OF DIGITAL FILTER

HARDWARE SIMULATION OF DIGITAL FILTERS IN THE RESIDUE NUMBER SYSTEM

Findings

CONCLUSION