High-Performance CdSe:In Nanowire Field-Effect Transistors Based on Top-Gate Configuration with High-κ Non-Oxide Dielectrics

Abstract

A dual-gate field-effect transistor (FET) based on the same single indium-doped CdSe nanowire using Si3N4 and SiO2 as top- and back-gate dielectrics, respectively, was fabricated. This dual-gate FET enabled direct comparison of the device performance of FETs in both top- and back-gate configurations. Remarkably, the field-effect mobility, peak transconductance, and Ion/Ioff ratio of the Si3N4 top-gate FET were 52, 142, and 2.81 × 105 times larger than the respective values of the SiO2 back-gate FET. Meanwhile, the threshold voltage and the subthreshold swing of the top-gate FET decreased to −1.7 V and 508 mV/decade, respectively, which are better than the best values ever obtained in FETs based on II−VI semiconductor nanomaterials including CdSe nanowires. The roles of device configurations and gate materials in the FET characteristics and the evaluation of electronic and transport properties of nanostructures based on that were discussed. Two kinds of basic logic circuits, “AND” and “OR”, were constructed with the top-gate transistors, which could also utilize light-input to realize a phototransistor action to take advantage of its photoresponse properties.