Highly Scalable 3-D Vertical FG NAND Cell Arrays Using the Sidewall Control Pillar (SCP)

Abstract

In this paper, we propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the sidewall control pillar (SCP). This novel cell consists of cylindrical FG and SCP with a line type control gate (CG) structure. For simplifying the process flow, we propose to fabricate the cylindrical SCP structure by using the self-aligned process with the deposition of the poly silicon pillar. In order to compensate the increase of the channel capacitance, we decrease the floating gate width by about 15nm, which is comparable thickness to recent charge trap layer, and adopt the high-k material for inter poly dielectric (IPD). As a result, we successfully demonstrate the program with 18V at Vth=4V and erase with 17V at Vth=-3V, that are comparable performances in comparison with the conventional FG NAND cells by using the device simulator. Moreover, using the proposed SCP NAND cell, the interference margin with cell space length has been successfully extended and the same vertical scaling as the charge trap (CT) type 3D NAND cell also can be realized for 2Xnm technology. Above all, the proposed cell has good potential for Terabit 3-D vertical NAND cell with high manufacturability.