Highly Efficient All‐Solution‐Processed Low‐Voltage Organic Transistor with a Micrometer‐Thick Low‐k Polymer Gate Dielectric Layer

Abstract

The development of organic thin‐film transistors (OTFTs) towards commercial viability must overcome a critical hurdle: achieving low operation voltage and high power efficiency with a fully printable device structure. This work realizes all‐solution‐processed low‐voltage OTFTs on a micrometer‐thick (1.16 μm) gate dielectric layer of very common material (commercial SU8 photoresist) by reducing the sub‐gap density of states at the channel. Being operated with a similar low voltage but at a gate dielectric capacitance of orders‐of‐magnitude smaller than that of conventional low voltage OTFTs, the fabricated device presents the best reported power efficiency. Logic circuits using this OTFT are shown to be able to run faster but consume significantly less power. Moreover, since being operated at a record low gate field of 0.05 MV cm−1 attributed to the thick dielectric layer, the device also exhibits several other attractive features such as large gate input impedance and the capability of sustaining high voltage operation. This device design would be an ideal solution to address the material and process issues for developing fully‐printable low voltage OTFTs with desired performance for the envisioned applications.