High-Level AMBA Monitoring Platform for SoC Architecture Exploration

Abstract

As a System on Chip (SoC) hardware complexity grows dramatically, it becomes more difficult to find the optimal SoC architecture with various hardware IPs. Accordingly, SoC architecture exploration should be performed before the chip-level implementation where various types of on-chip interconnect topology are compared according to the on-chip traffic patterns from a number of hardware IPs in terms of area, transaction latency, power consumption, etc. In this paper, we propose a high-level AMBA (Advanced Microcontroller Bus Architecture) Monitoring Platform where various traffic statistics can be obtained with C++ modeling using open-source Verilator. For the evaluation, we built the baseline SoC platform with Arm Cortex-M4F CPU core and various hardware IPs. With the proposed high-level AMBA monitoring platform, the high-level C++ modeling of on-chip traffic analysis allows to find optimal AMBA on-chip interconnects in the early stages with fast analysis time based on the on-chip traffic analysis.