High-k Dielectrics for Ge, III-V and Graphene MOSFETs

Abstract

It is well known that the existence of a high quality oxide on Si has been key to the success of Si metal oxide semiconductor field effect transistors (MOSFETs). Replacing SiO2 with high-k dielectrics in order to reduce gate tunneling currents has proven to be challenging, though it is now a manufacturable technique. Scaling of Si CMOS logic devices to the next level has led to a flurry of activity in enhanced channel mobility MOSFETs, using semiconductors from Column IV such as Ge and graphene, and III-V materials such as GaAs, InGaAs and InP. Since these materials lack a high-quality native oxide, integrating high-k gate dielectrics represents a marriage of necessity and convenience. It is known that atomic layer deposition (ALD) offers precise control over the uniformity and thickness of the deposited high-k films through a self-limiting reaction. Furthermore, ALD can potentially offer the advantage of reducing native oxides by appropriate engineering of the precursor chemistry. Nevertheless, integrating ALD high-k on Ge, graphene and III-V materials necessitates the use of an effective chemical surface treatment protocol. This is to alter the surface properties in order to ensure full surface coverage from the beginning of ALD runs, while preventing the re-oxidation.