High-voltage LDMOS transistors fully compatible with a deep-submicron 0.35 μm CMOS process

Abstract

This work presents the design of LDMOS transistors fully compatible with a standard CMOS process, only requiring mask layout manipulation. A conventional 0.35 μm CMOS process was elected to demonstrate the viability of the approach. The prototyped LDMOS transistor exhibits a breakdown voltage of 24 V, which represents an improvement of 31% when compared with the high-voltage extended-drain NMOS available in the process library, while other static parameters remain in the same range. Furthermore, this solution enables the CMOS integration of a high-voltage pass-transistor, as a consequence of the formation of an isolated lightly doped p-type region inside the n-well.