High-throughput process chain for single electron transistor devices based on field-emission scanning probe lithography and Smart Nanoimprint lithography technology

Abstract

Next generation electronic devices like single electron transistors (SETs) operating at room temperature (RT) demand for high-resolution patterning techniques and simultaneously cost-effective, high-throughput manufacturing. Thereby, field-emission scanning probe lithography (FE-SPL) is a direct writing method providing high-resolution and high-quality nanopatterns. SET devices prepared by FE-SPL and plasma etching at cryogenic substrate temperature were shown to operate at RT [C. Lenk et al., Microelectron. Eng. 192, 77 (2018); Z. Durrani, M. Jones, F. Abualnaja, C. Wang, I. W. Rangelow, M. Kaestner, S. Lenk, C. Lenk, and A. Andreev, J. Appl. Phys. 124, 144502 (2018); I. W. Rangelow et al., J. Vac. Sci. Technol. B 34, 06K202 (2016)]. Nevertheless, FE-SPL lacks in writing speed and large area manufacturing capability required for industrial device manufacturing. This can be overcome by combining FE-SPL with nanoimprint lithography (NIL), which enables the replication of high-resolution features on large areas and provides high throughput. In this work, the authors will review a high-throughput process chain for RT-SET fabrication based on reproducing FE-SPL prepared masters by NIL and etching.