Abstract
Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.
Highlights
Science of cryptography is the information protection technique to encrypt, store and secure data when transmitted, to prevent reading of private information by intruders or public
The Secure Hash Algorithm 3 (SHA-3) algorithm has been implemented in the Keccak hash function using the VHDL programming language and the Nios II processor was used for all Keccak algorithm output lengths (224, 256, 384 and 512)
By the synthesis report we extracted the detailed results for the entire system design we had implemented the SHA-3 algorithm with the Keccak hash function
Summary
Science of cryptography is the information protection technique to encrypt, store and secure data when transmitted, to prevent reading of private information by intruders or public. Technologies 2020, 8, 15 same general hash function family of SHA-1 so that similar cryptanalysis methods could succeed in the attack [8]. This has led the National Institute of Standards and Technology (NIST) to look for new and safer hashing algorithms. We designed the SHA-3 algorithm in the Keccak hash function for all proposed output lengths (224, 256, 384 and 512) in the Intel FPGA Arria 10 GX (10AX115N2P45E1SG). We researched on the optimization strategy for the throughput and efficiency of all output lengths of the Keccak algorithm (SHA-3).
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