Hardware implementation of a SHA-3 application-specific instruction set processor

Abstract

Secure Hash Algorithm 3 (SHA-3) based on the Keccak algorithm is the new standard cryptographic hash function announced by the National Institute of Standards and Technology (NIST). Hash functions are a ubiquitous computing tool that is commonly used in security, authentication, and many other applications. The calculation of SHA-3 is very computational-intensive limiting its applicability on RISc processors used in modern embedded systems and Systems on chips (Socs). In this work, we study the SHA-3 computation bottlenecks on a 32-bit RISC processor and introduce two Application Specific Instruction Set Processor (ASIP) architectures to speedup SHA-3 computation on the 32-bit MIPS processor. Two ASIP architectures namely native datapath and coprocessor-based ASIPs are developed with the aid of codasip Studio, implemented and evaluated on a Xilinx Virtex-6 FPGA. Compared to the reference SHA-3 execution on MIPS, the evaluation results show a 25% and 61.4% speedup for the native and coprocessor-based ASIPs at the expense of a 8.6% and 25.8% resource overheads, respectively.