High throughput dynamic dual entropy source true random number generator based on FPGA

Abstract

True Random Number Generator (TRNG), a primitive language of hardware security, plays a significant role in key generation, data encryption, initialization vectors, and other situations. To address the problem of incompatibility between low resource overhead and high throughput of TRNG, a dual entropy source TRNG architecture based on Field Programmable Gate Array (FPGA) is proposed, whose entropy sources include clock jitter and metastability. Different from other TRNGs that use multiplexers (MUX), it also uses the ring oscillators and path delay differences to dynamically convert the oscillation frequency of the multiplexer ring oscillator (MRO), thus increasing the randomness of the entropy source. This architecture is implemented on Xilinx Artix-7 and Kintex-7 FPGAs and has been tested with NIST tests, AIS-31 tests, as well as voltage and temperature tests, and has been compared with other up-to-date TRNGs. The experimental results show that the MRO-TRNG only requires 10 LUTs, 2 DFFs, and 1 MUX, providing a throughput of up to 300 Mbps.