Abstract

 
 
 This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this design is to achieve high throughput rates combined with low hardware consumption. The architecture was described in VHDL and synthesized to the EP2S60F1020C3 Altera Stratix II FPGA and to the TSMC 0.18μm Standard Cell technology. The architecture is able to operate at 364.2 MHz as a maximum operation frequency. At this frequency, the architecture is able to process 117 QHDTV frames (3840x2048 pixels) per second. The designed architecture can be used in low power and low cost applications, since it can process high resolution in real time even with very low operation frequencies and with low hardware consumption. In the comparison with related works, the designed Q module achieves the best results of throughput and hardware consumption.
 
 
Highlights
The H.264/AVC is the newest video coding standard [1]
Code routines were inserted in the JM 16.0 Reference Software [7] of the H.264/AVC Standard, in order to take the input and output data for the quantization module, which were used as golden model in this design
The architecture is able to operate at 346.2 MHz, overcoming in 19% the maximum frequency achieved by the FPGA synthesis
Summary
The H.264/AVC is the newest video coding standard [1]. It was developed by the union of experts from ISO/IEC and ITU-T intending to double the compression rates when compared with previous standards.Video coding is extremely important considering the amount of data in the high definition videos. The H.264/AVC is the newest video coding standard [1]. It was developed by the union of experts from ISO/IEC and ITU-T intending to double the compression rates when compared with previous standards. Video coding is extremely important considering the amount of data in the high definition videos. The H.264/AVC standard has efficient tools to reduce the computational representation of these videos. The H.264/AVC encoders have high computational complexity as well. This way, hardware solutions are necessary, at least in the current technology, when real time processing (24 to 30 frames per second) and high resolutions videos are required
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