Abstract
In this paper, a low hardware consumption design of elliptic curve cryptography (ECC) over GF(p) in embedded applications is proposed. The adder-based architecture is explored to reduce the hardware consumption of performing scalar multiplication (SM). The Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved and implemented with two full-word adder units. The full-word register units for data storage are also optimized. The design is based on two full-word adder units and twelve full-word register units of pipeline structure and was implemented on Xilinx Virtex-4 platform. Design Compiler is used to synthesized the proposed architecture with 0.13 μm CMOS standard cell library. For 160, 192, 224, 256 field order, the proposed architecture consumes 5595, 7080, 8423, 9370 slices, respectively, and saves 17.58∼54.93% slice resources on FPGA platform when compared with other design architectures. The synthesized result uses 35.43 k, 43.37 k, 50.38 k, 57.05 k gate area and saves 52.56∼91.34% in terms of gate count in comparison. The design takes 2.56∼4.07 ms to perform SM operation over different field order under 150 MHz frequency. The proposed architecture is safe from simple power analysis (SPA). Thus, it is a good choice for embedded applications.
Highlights
IntroductionElliptic curve cryptography (ECC) is an asymmetric cryptography proposed in 1986 by Miller [1]
Elliptic curve cryptography (ECC) is an asymmetric cryptography proposed in 1986 by Miller [1]and Koblitz [2]
point addition (PA) operation consists of one Modular inversion (MI), two modular multiplication (MM), and six Modular addition (MA)/modular subtraction (MS) operations, whereas point doubling (PD) operation needs one MM and two MA/MS more operations than PA
Summary
Elliptic curve cryptography (ECC) is an asymmetric cryptography proposed in 1986 by Miller [1]. The main advantage of ECC is that it uses a smaller key than some other methods, such as the RSA encryption algorithm, to provide a comparable or higher level of security. Adder-based architecture uses Interleaved Multiplication algorithm [20]. Design in [8] is based on modified Montgomery multiplication algorithm using an r-bit × r-bit multiplier. An adder-based architecture with low hardware consumption over GF(p) is proposed. Interleaved Modular Multiplication Algorithm and Binary Modular Inversion Algorithm are improved carefully to make full use of hardware source of adder and register. The architecture is flexible and safe from SPA The parameters, such as prime value p, elliptic curve point P and scalar value k, can be deployed without hardware reconfiguration.
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