High throughput and energy efficient linear phase FIR filter architectures

Abstract

High throughput, low complex and energy efficient linear phase FIR filter structures with low latency are highly desirable for most of the portable signal processing applications. Improving the throughput and energy efficiency while ensuring low latency and complexity is a difficult problem due to the trade-off between performance metrics. To this end, the design of linear phase filter based on the application of retiming and pipelining is proposed. The CPD, PDP, ADP and ELT of the proposed 16-tap linear phase FIR filter is reduced by 64.83%, 80.1%, 61.58%, and 62.49% respectively in comparison with FIR filter using flexible retiming and by 18.29%, 30.99%, 16.56%, and 12.82% respectively in comparison with the recent retiming based high throughput FIR filter. The 16-tap ECG denoising filter developed from the proposed filter structure provides excellent performances in terms of CPD, PDP, ADP and ELT as the algorithmic transformations are applied to an exact multiplier-less linear phase filter structure. It filters out PLI of 50 Hz, its harmonics and high frequency noises while providing improved denoising performances. The CPD, PDP, ADP and ELT of the proposed multiplier-less ECG denoising filter is reduced by 82.44%, 97.55%, 93.51%, and 81.27% respectively in comparison with a typical 17-tap FIR notch filter and by 70.06%, 99.82%, 99.68%, and 98.12% respectively in comparison with a typical Bartlett window based 256-tap FIR notch filter. Structural model VHDL coding is used for developing filters. For synthesis, Cadence software with gpdk 45 nm standard cell library is used and for simulation modelsim is used.