High temperature processing of ferroelectric thin films using interconnect wafer technology

Abstract

There is interest in ferroelectric thin films for uncooled IR detector applications. Currently the processing of these devices takes a fully integrated approach where the thin films are deposited directly onto underlying CMOS readout circuitry, thereby imposing severe limits on the thermal budget available for the crystallisation of the ferroelectric material. This is incommensurate with obtaining the best ferroelectric properties from materials such as lead scandium tantalate (PST) which requires elevated temperature processing to attain the highest merit figures for IR detection. In this paper thin film PST processed within the CMOS survivability envelope will be compared to that processed at temperatures up to 850°C. A novel interconnect wafer technology will be outlined which enables processing to be extended to such temperatures. It will be shown that elevated temperature processing of the PST film can result in dramatic improvement of the materials merit figure for IR detection