Abstract
The main challenging areas in VLSI are performance, cost, testing, area, reliability, delay and power. The demand for portable computing devices and communications system are increasing rapidly. These applications require low power dissipation and low area with high speed for VLSI circuits. Hence it is important aspect to optimize power, area and delay .So these constraints optimization became one of the main challenges. In this paper a Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm are designed with area, delay and power efficient. To optimize these structures a data flow HDL model is preferred because of consuming less resources when compare with other modeling schemes. This architecture is authorized in Verilog. Behavior simulation is done by using the ISE simulator and synthesis can be done by using the synthesis Xilinx ISE 9.2i
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