Abstract
The authors describe a new high-performance self-timed circuit for asynchronous square rooting. The new architecture is based on a modified nonrestoring algorithm. An asynchronous pipelined cellular array without auxiliary system for the identification of exceptions will be demonstrated. The self-timing approach allows the whole performance to be greatly improved with respect to synchronous implementation, causing acceptable area overheads.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
