SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation

Abstract

A structural delay-insensitivity verification analysis method, SDIVA, is proposed for asynchronous systolic arrays in dual-rail threshold logic style. The SDIVA method employs symbolic delays for all output evaluation paths and works at the behavioral specification level. For bit-level pipelined systolic arrays, which have data-dependent early output evaluation in one-dimension, SDIVA method reduces the verification analysis task to examination of three adjacent systoles so that by analyzing all possible early/late output evaluation scenarios on three systoles, the delay-insensitivity of a complete systolic array could be verified at once, regardless of the array dimensions. Delay-insensitivity violations are located and corrected at structural level, without diminishing the early output evaluation benefits. Since symbolic delays are used without imposing any timing assumptions on the environment; the SDIVA method is technology independent and robust against all physical and environmental variations.