High speed SAD architecture for variable block size motion estimation in HEVC encoder

Abstract

Motion Estimation (ME) is the most time-consuming process in High Efficient Video Coding (HEVC) encoder. The calculation of Sum of Absolute Difference (SAD) between current block and reference block creates the highest computing load in ME process. Moreover, the block size in HEVC can expand up to 64×64 for real time applications, hence the complexity of variable block size SAD calculation increases sharply, and the calculation requires a lot of hardware resources. In this paper, a novel high speed SAD architecture for variable block size ME in HEVC encoder is proposed to reduce the hardware usage as well as the calculation time. The design is integrated with the other parts to make Integer Motion Estimation block as well. The evaluation results of the synthesized system implemented in 65nm Virtex-5 FPGA show that the max frequency of the proposed architecture obtains 190.785 MHz.