High-speed redundant reciprocal approximation

Abstract

This paper presents a fast implementation for reciprocal approximation, that can compute a redundant reciprocal of a normalized number with a precision of 2 −28 in roughly 16–17 logic levels. Moreover, a less accurate, but much cheaper implementation is proposed. The redundant representation of the reciprocal can directly be fed into a common Booth multiplier. This allows to implement IEEE floating-point division with correct rounding in all rounding modes with a latency of 7 clock cycles in double precision and 4 clock cycles in single precision. We also consider fast redundant compressions from carry–save representations to redundant Booth-digit representations.