Abstract
AbstractThe newly proposed BiCMOS technology [4] is based on the idea of realizing an LSI with high‐speed and low‐power consumption properties, by combining the bipolar and CMOS technologies in the basic circuit. It was demonstrated in [4] that the designed performance can be realized for logic circuit. This paper reports on the application of the technique to the gate array, where the circuit is constructed by 1.3 μm Hi‐BiCMOS technology and the overall performance as LSI is evaluated experimentally. First, three kinds of master chips suited to the high‐speed processor such as a minicomputer are designed. Among those, a master chip was selected and developed, which includes a multiport RAM and is applicable to the arithmetic logic unit containing a register file. The internal RAM has a structure of 4 kbit and 3‐port, and the access time is less than 10 ns. A basic cell structure to construct the logic circuit by a combination of bipolar and CMOS technologies is devised. A 2‐input NAND gate with a typical delay of 0.45 ns was realized. This type of gate array will be useful in the devices such as those in minicomputer and communication systems, where a high‐speed operation is required.
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