High-speed GaAs multipliers fabricated with a high-yield 0.4- mu m process

Abstract

A 0.4- mu m GaAs IC fabrication process which demonstrates excellent yields for direct-coupled FET logic circuits of up to 5000 gates for high-speed LSI digital applications is discussed. The refractory self-aligned gate process uses 1- mu m stepper lithography. An n/sup +//n'/buried-p structure results in superior threshold voltage uniformity for a 0.4- mu m gate length, with sigma V/sub T/ as low as 8 mV over 3-in wafers. Simple parallel array multipliers were used for process validation. Die-sort yields for a 16-b*16-b multiplier are typically better than 55%, and as high as 88%. A 5000-gate 20-b*20-b multiplier shows yield as high as 61%, and a Poisson yield model predicts a die-sort yield of 30% for a 10000-gate circuit. Multiplication times of 3.6 ns for the 16-b*16-b and 4.5 ns for the 20-b*20-b multiplier have been measured. The corresponding loaded gate delay and power-delay product are 46 ps/gate and 40 fJ, respectively, at room temperature.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>