High speed FinFET domino logic circuits with independent gate-biased double-gate keepers providing dynamically adjusted immunity to noise

Abstract

Scaling of single-gate bulk MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the subthreshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates this limitation by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. With the variable threshold voltage keeper circuit technique the evaluation speed is enhanced by up to 55% while reducing power consumption by up to 57% as compared to a standard domino logic circuit designed for similar noise margin in a 32 nm FinFET technology.