Abstract
Implementation of a FFT processor using pipelining and folding techniques which is achieved by reducing number of functional units, registers and multiplexers. The pipelining and parallel processing techniques deals with the reducing the critical path which in turns increases the speed of the processor, in order achieve high speed, special kind of multipliers and adders are used. The folding transformation is used to systematically determine the control circuits in DSP architectures where multiple algorithm operations (such as addition operations) are time multiplexed to a single functional unit. By executing multiple algorithm operations on a single function unit, the number of functional units in the implementation is reduced resulting in an integrated circuit with low silicon area.
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