High speed and low sensitive current-mode CMOS perceptron

Abstract

The paper presents a prototype of a perceptron network working in the current mode, with a digital interface for applications in analog-to-digital systems. The presented implementation makes it possible to create a network using the standard nanometer CMOS technology, to use a row strategy for designing a topography, as well as to place an analog network IPcore on a silicon substrate, common with the digital part. The work introduces an implementation of a CMOS axon with a monotonic, differentiable and sigmoid activation function. It also introduces an implementation of a dendrite with a fully digital interface. The obtained dendrite weight mapping error was 0.072%. The article discusses routing neurons based on using weight values including an elimination of the CMRR concurrent component and reducing power consumption. The work presents a strategy for programming weights including completely eliminating the mismatch process. The works included a mismatch analysis of the operation of the network and a verification of the signal processing accuracy. A sample 7.8MHz multi-layer implementation with 16 weights yielded precision=94.62%, and a 5Ms/s multi-layer implementation of 1098 weights: precision=93.28%.