High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

Abstract

In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA) architectures including a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. IRredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of a multiplexer-based logic to reduce the number of gates and to achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures. Experimental results show that the hybrid CSLAs lead to lowest area-delay product and energy-delay product among all the proposed and previous designs in a wide range of 8-bit to 128-bit adder size. In fact, 10–48% reduction in area-delay product and 8–65% reduction in energy-delay product are achieved compared to previous designs. Moreover, the hybrid CSLAs outperform the best existing design with respect to all three parameters of area, delay and energy.