High Robust and Low Cost Soft Error Hardened Latch Design for Nanoscale CMOS Technology

Hong-Chen Li,Li-Yi Xiao,Xue-Bing Cao,Jie Li

doi:10.1109/icsict.2018.8565650

High Robust and Low Cost Soft Error Hardened Latch Design for Nanoscale CMOS Technology

Hong-Chen Li, Li-Yi Xiao + Show 2 more

https://doi.org/10.1109/icsict.2018.8565650

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Publication Date: Oct 1, 2018

Citations: 5

Affiliation: Harbin Institute of Technology

#High Soft Error #Latch Design + Show 8 more

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Abstract

We propose a high robust and low cost soft error hardened latch design applied to SMIC 65nm technology in this paper. With the method of SET filtering technique and inter-latching structure, the proposed latch can self-recover from SEUs and filter SETs. Simulation results have indicated that the proposed latch design possess high reliability and lowest PDP.

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